1. Field of the Invention
The present invention relates to a CMUT and, more particularly, to a high frequency CMUT.
2. Description of the Related Art
A capacitive micromachined ultrasonic transducer (CMUT) is a semiconductor-based ultrasonic transducer that utilizes a change in capacitance to convert received ultrasonic waves into an electrical signal, and to convert an alternating electrical signal into transmitted ultrasonic waves.
FIGS. 1A-1C show views that illustrate a prior-art CMUT array 100. FIG. 1A shows a plan view of CMUT array 100, while FIG. 1B shows a cross-sectional view of CMUT array 100 taken along line 1B-1B of FIG. 1A, and FIG. 1C shows a cross-sectional view of CMUT array 100 taken along line 1C-1C of FIG. 1A.
As shown in FIGS. 1A-1C, CMUT array 100 has three CMUT elements 102 arranged in a single row, where each CMUT element 102 has 12 CMUT cells 104 arranged in an array three CMUT cells wide by four CMUT cells long. Further, each adjacent pair of CMUT elements 102 has a minimum spacing X of 16 μm, while each adjacent pair of CMUT cells 104 have a minimum spacing Y of 5 μm.
CMUT array 100 also has a conventionally-formed semiconductor substrate 110, and a post oxide structure 112 that touches semiconductor substrate 110. Semiconductor substrate 110 has a top surface which, in turn, has a number of spaced-apart CMUT surface regions 113. Further, semiconductor substrate 110 is heavily doped to have a resistance of 0.01 Ω/cm or less. Post oxide structure 112 horizontally surrounds, but does not cover, each CMUT surface region 113. In addition, post oxide structure 112 has substrate contact openings 114 that extend completely through post oxide structure 112 to expose semiconductor substrate 110.
As additionally shown in FIGS. 1A-1C, CMUT array 100 includes a number of cell oxide structures 116, a corresponding number of silicon membranes 120, and a corresponding number of vacuum-sealed cavities 122. The cell oxide structures 116 touch the CMUT surface regions 113 on the top surface of semiconductor substrate 110. The silicon membranes 120 touch the top surface of post oxide structure 112 and lie over and spaced apart from the cell oxide structures 116. The vacuum-sealed cavities 122, which are horizontally surrounded by post oxide structure 112, lie vertically between the cell oxide structures 116 and the silicon membranes 120. Each of the silicon membranes 120 is approximately 2.2 μm thick.
CMUT array 100 also includes a number of aluminum plates 126 (which can optionally include copper). Each aluminum plate 126 touches and covers the top surfaces of a group of silicon membranes 120, where an aluminum plate 126 and a group of silicon membranes 120 are part of a CMUT element 102. The aluminum plates 126 reduce the sheet resistances of the silicon membranes 120, and provide low-resistance paths to bond pad regions 128 on the top surfaces of the aluminum plates 126. For example, a 1500 Å-thick aluminum plate has a sheet resistance of approximately 180 mΩ/square.
Further, CMUT array 100 includes a number of aluminum bond pads 130 (which can optionally include copper) that lie within the substrate contact openings 114 to touch semiconductor substrate 110. In addition, CMUT array 100 includes a passivation layer 132 approximately 2000 Å thick that touches and lies over post oxide structure 112, the aluminum plates 126, and the aluminum bond pads 130. Passivation layer 132, in turn, has a number of bond pad openings 136 that expose the aluminum bond pads 130, and a number of bond pad openings 138 that expose the bond pad regions 128 on the top surfaces of the aluminum plates 126.
The silicon membranes 120, the overlying portions of the aluminum plates 126, and the overlying portions of passivation layer 132 form a number of membrane stacks 140 that lie directly over a corresponding number of vacuum-sealed cavities 122. The membrane stacks 140, along with the vacuum-sealed cavities 122 and the cell oxide structures 116, form the CMUT cells 104. Further, CMUT array 100 has an acoustic dampening structure 142 that touches the bottom surface of semiconductor substrate 110.
In operation, a first bias voltage is placed on semiconductor substrate 110, which functions as a first capacitor plate, and a second bias voltage is placed on the silicon membranes 120, which function as second capacitor plates. Thus, the voltages across the capacitor plates lie across the vacuum-sealed cavities 122. When used as a receiver, an ultrasonic wave causes the membrane stacks 140 to vibrate. The vibration varies the capacitance across the first and second capacitor plates, thereby generating an electrical signal that varies as the capacitance varies.
When used as a transmitter, an alternating electrical signal applied across the biased first and second capacitor plates causes the membrane stacks 140 to vibrate which, in turn, transmits ultrasonic waves. The rate or frequency at which a membrane stack 140 vibrates depends on a number of factors, including the lateral dimensions of vacuum-sealed cavity 122, and the stiffness of membrane stack 140. The stiffness of membrane stack 140, in turn, depends in part on the thickness of membrane stack 140.
In addition to transmitting ultrasonic waves outward, ultrasonic waves are also transmitted backward towards the bottom surface of semiconductor substrate 110. These backward ultrasonic waves can resonate within semiconductor substrate 110 depending on the thickness of semiconductor substrate 110 and the frequency of operation, and can interfere with the quality of the resultant image. Acoustic dampening structure 142 absorbs and dampens the ultrasonic waves in semiconductor substrate 110.
FIGS. 2A-2N show cross-sectional views that illustrate a prior-art method 200 of forming a CMUT structure. As shown in FIG. 2A, method 200 utilizes a conventionally-formed single-crystal silicon wafer 210. Silicon wafer 210 has rows and columns of die-sized regions, and one or more CMUT cells can be simultaneously formed in each die-sized region.
For simplicity, rather than showing the simultaneous formation of two or more identical CMUT cells, FIGS. 2A-2N illustrate the formation of a CMUT structure that has a single CMUT cell. FIGS. 2A-2N also illustrate the formation of a bond pad structure. Further, silicon wafer 210 has a top surface which, in turn, has a CMUT surface region 211. In addition, silicon wafer 210 is heavily doped to have a resistance of 0.01 Ω/cm or less.
Method 200 begins by forming a patterned photoresist layer on the top surface of silicon wafer 210 in a conventional manner. After the patterned photoresist layer has been formed, the top surface of silicon wafer 210 is etched for a predefined time to form two or more front side alignment marks.
If a wet etchant is used, the resulting structure is rinsed following the etch. After the rinse, the patterned photoresist layer is conventionally removed, such as with an ash plus a solvent clean. Following the removal of the patterned photoresist layer, the resulting structure is cleaned to remove organics, such as with a Piranha etch (e.g., using a solution of 50 H2SO4: 1 H2O2 @ 120° C. removes approximately 240 nm/minute).
Next, as shown in FIG. 2A, method 200 continues by forming a post oxide structure 212 approximately 8500 Å thick on the top surface of silicon wafer 210 using the well-known local oxidation of silicon (LOCOS) process (e.g., the formation of a patterned hard mask followed by 1050° C. steam for 140 minutes). Post oxide structure 212 has a cell opening 213 (where the hard mask was placed and where a CMUT cell will be formed) approximately 60 μm wide that exposes and horizontally surrounds CMUT surface region 211. The LOCOS process also forms a backside oxide structure 214 that touches the bottom surface of silicon wafer 210 at the same time.
Following this, as shown in FIG. 2B, a cell oxide layer 216 approximately 4550 Å thick is grown in cell opening 212A on CMUT surface region 211 on the top surface of silicon wafer 210. The growth of cell oxide layer 216 causes post oxide structure 212 to continue growing, reaching a thickness of approximately 10500 Å.
After cell oxide layer 216 has been formed, as shown in FIG. 2C, a silicon-on-oxide (SOI) wafer 220 is fusion bonded to the top surface of post oxide structure 212 in a vacuum to form a vacuum-sealed cavity 222. Cavity 222, in turn, has a depth, which is measured vertically from the top surface of cell oxide layer 216 to the top surface of post oxide structure 212, of approximately 3100 Å.
SOI wafer 220 has a handle wafer 224, a buried insulation layer 226 approximately 1.1 μm thick that touches handle wafer 224, and a single-crystal silicon substrate structure 228 approximately 2.2 μm thick. Substrate structure 228, in turn, has a first surface that touches buried insulation layer 226, and a second surface that touches post oxide structure 212.
After substrate structure 228 has been fusion bonded to post oxide structure 212, as shown in FIG. 2D, handle wafer 224 is removed in a conventional manner, followed by the conventional removal of insulation layer 226. Next, as shown in FIG. 2E, a patterned photoresist layer 230 is formed on the first surface of substrate structure 228.
Once patterned photoresist layer 230 has been formed, as shown in FIG. 2F, the exposed region of substrate structure 228 is etched to form a CMUT membrane 232. The etch also re-exposes the alignment marks. (Alignment marks can alternately or additionally be formed on the backside of silicon wafer 210.) Patterned photoresist layer 230 is then removed in a conventional manner.
As shown in FIG. 2G, after the removal of patterned photoresist layer 230, a patterned photoresist layer 240 is formed on post oxide structure 212 and CMUT membrane 232. Once patterned photoresist layer 240 has been formed, as shown in FIG. 2H, the exposed region of post oxide structure 212 is etched until silicon wafer 210 has been exposed. The etch forms a substrate contact opening 241 that is approximately 50 μm wide. Patterned photoresist layer 240 is then removed in a conventional manner.
Following the removal of patterned photoresist layer 240, as shown in FIG. 2I, an aluminum layer 242 (which can optionally include copper) approximately 1500 Å thick is deposited to touch silicon wafer 210, post oxide structure 212, and CMUT membrane 232. After this, a patterned photoresist layer 250 is formed on aluminum layer 242.
Next, as shown in FIG. 2J, the exposed region of aluminum layer 242 is etched to form an aluminum bond pad 252 that extends through post oxide structure 212 to touch silicon wafer 210, and an aluminum plate 254 that touches and covers the top surface of CMUT membrane 232. Patterned photoresist layer 250 is then removed in a conventional manner.
As shown in FIG. 2K, after patterned photoresist layer 250 has been removed, a passivation layer 256 approximately 2000 Å thick is formed to touch and lie over post oxide structure 212, aluminum bond pad 252, and aluminum plate 254. Passivation layer 256 protects aluminum plate 254 from being damaged during subsequent packaging steps. CMUT membrane 232 and the portions of aluminum plate 254 and passivation layer 256 that lie over vacuum-sealed cavity 222 form a membrane stack 258. Once passivation layer 256 has been formed, a patterned photoresist layer 260 is formed on passivation layer 256.
After this, as shown in FIG. 2L, the exposed regions of passivation layer 256 are etched to form a bond pad opening 261 that exposes aluminum bond pad 252, and a bond pad opening, like a bond pad opening 138 in FIG. 1A, that exposes a bond pad region of aluminum plate 254. As shown in FIG. 2M, patterned photoresist layer 260 is then removed in a conventional manner.
Next, the resulting structure is flipped over for processing, and backside oxide structure 214 is removed in a conventional manner. For example, backside oxide structure 214 can be removed using chemical mechanical polishing. Alternately, backside oxide structure 214 can be removed using a single-sided wet etch, such as a SEZ etch by SEZ Austria GmbH, Draubodenweg 29, A-9500 Villach, Austria.
Following the removal of backside oxide structure 214, an acoustic damping structure 262, such as a tungsten epoxy mixture, is deposited onto the bottom side of silicon wafer 210 to form, as shown in FIG. 2N, a CMUT structure 264 with a CMUT cell 270. Silicon wafer 210 is then diced to form a number of individual die that each has one or more CMUT elements and cells.
Each CMUT cell 270 is designed to have a fractional bandwidth (FB) greater than 100% and a Q that is less than one. In addition, CMUT membrane 232 and the overlying portions of aluminum plate 254 and passivation layer 256 (membrane stack 258) are configured to vibrate at a maximum frequency of approximately 20 MHz.
One limitation of CMUT cell 270 is the ability to operate at higher frequencies (F0˜40 MHz) while maintaining a fractional bandwidth greater than 100% and a Q less than one. A maximum frequency of 20 MHz is suitable for some contact or near contact body imaging applications, like echo cardiograms, but higher frequency operation would enable higher resolution medical imaging applications and non-destructive evaluation applications, such as the imaging of structural defects or the detection of frequency shifts due to chemical absorption. These applications require a maximum frequency of 40 MHz or more.
In order to operate at higher frequencies (>20 MHz) while maintaining the desired fractional bandwidth (>100%) and Q (<1), the thickness of membrane stack 258 must be reduced. Reducing the thickness of membrane stack 258 changes the frequency which, in turn, requires that the lateral dimension of vacuum-sealed cavity 222 be reduced accordingly.
To reduce the thickness of membrane stack 258, the thickness of silicon substrate structure 228, which becomes CMUT membrane 232, can be reduced. For example, the thickness of silicon substrate structure 228 can be reduced from 2.2 μm to 1 μm while maintaining structural stability. However, even a thickness of 1 μm is too large for efficient high frequency operation.
Additionally, the thickness of aluminum plate 254 can also be reduced to reduce the thickness of membrane stack 258. However, reducing the thickness of aluminum plate 254 is undesirable because the sheet resistance of aluminum plate 254 increases as the thickness of aluminum plate 254 is reduced.
For example, a 250 Å thick aluminum plate has a sheet resistance of approximately 1 Ω/square as compared to the approximate 180 mΩ/square sheet resistance of a 1500 Å thick aluminum plate. In a CMUT array, where the bond pad region lies a substantial distance away from the CMUT cells, it is undesirable for charge carriers to move this long a distance through a material that has a sheet resistance of 1 Ω/square.
With respect to passivation layer 256, the thickness of passivation layer 256 cannot be meaningfully reduced to reduce the thickness of membrane stack 258. This is because passivation layer 256 protects aluminum plate 254 during subsequent packaging steps. As a result, the thickness of passivation layer 256 is determined by the level of protection that is required, and may need to be increased if the thickness of aluminum plate 254 is reduced.
Thus, once the thickness of CMUT membrane 232 has been reduced as much as possible, there is still a need for an approach to further increase the maximum vibrational frequency of membrane stack 258.